? semiconductor components industries, llc, 2000 march, 2000 rev. 2 1 publication order number: mc10h646/d
the mc10h/100h646 is a single supply, low skew translating 1:8 clock driver. devices in the motorola h600 translator series utilize the 28lead plcc for optimal power pinning, signal flow through and electrical performance. the single supply h646 is similar to the h643, which is a dual supply 1:8 version of the same function. the h646 was designed specifically to drive series terminated transmission lines. special techniques were used to match the high and low output impedances to about 7ohms. this simplifies the choice of the termination resistor for series terminated applications. to match the high and low output impedances, it was necessary to remove the standard i os limiting resistor. as a result, the user should take care in preventing an output short to ground as the part will be permanently damaged. the h646 device meets all of the requirements for driving the 60 and 66mhz pentium microprocessor. the device has no pll components, which greatly simplifies its implementation into a digital design. the eight copies of the clock allows for pointtopoint clock distribution to simplify board layout and optimize signal integrity. the h646 provides differential pecl inputs for picking up low skew pecl clocks from the backplane and distributing it to ttl loads on a daughter board. when used in conjunction with the mc10/100e111, very low skew, very wide clock trees can be designed. in addition, a ttl level clock input is provided for flexibility. note that only one of the inputs can be used on a single chip. for correct operation, the unused input pins should be left open. the output enable pin forces the outputs into a high impedance state when a logic 0 is applied. the output buffers of the h646 can drive two series terminated, 50 w transmission lines each. this capability allows the h646 to drive up to 16 different pointtopoint clock loads. refer to the applications section for a more detailed discussion in this area. the 10h version is compatible with mecl 10h ? ecl logic levels. the 100h version is compatible with 100k levels. ? pecl/ttlttl version of popular eclinps ? e111 ? low skew ? guaranteed skew spec ? tristate enable ? differential internal design ? v bb output ? single supply ? extra ttl and ecl power/ground pins ? matched high and low output impedance ? meets specifications required to drive the pentium ? microprocessor http://onsemi.com device package shipping ordering information mc10h646fn plcc28 37 units/rail marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 10h646 awlyyww 1 mc100h646fn plcc28 37 units/rail
mc10h646, mc100h646 http://onsemi.com 2 0 100 200 300 400 500 600 700 0 20 40 60 80 100 120 p dynamic = c l ? v swing v cc p total = p static + p dynamic ivt q3 ognd q2 ovt q1 ognd q0 q4 ogn d q5 ovt q6 ogn d q7 tclk 1 en ivt ignd vcce vcce vbb eclk 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 pinout: 28lead plcc (top view) ignd eclk vee vee vee ognd ovt ignd ivt v ee v cce eclk, eclk v bb q0q7 en ttl output ground (0v) ttl output v cc (+5.0v) internal ttl gnd (0v) internal ttl v cc (+5.0v) ecl v ee (0v) ecl ground (5.0v) differential signal input (pecl) v bb reference output signal outputs (ttl) tristate enable input (ttl) pin function pin names figure 1. output structure internal ttl ground ignd01 ognd0 q0a ovt01 ivt01 internal ttl power q0 q1 q2 q3 q4 q5 q6 q7 tclk eclk eclk en logic diagram figure 2. power versus frequency (typical) frequency, mhz power, mw power versus frequency per bit 300pf 200pf 100pf 50pf no load truth table tclk eclk eclk en q gnd gnd h l x l h gnd gnd x h l gnd gnd x h h h h l l h h l z l = low voltage level; h = high voltage level; z = tristate
mc10h646, mc100h646 http://onsemi.com 3 dc characteristics (ivt = ovt = vcce = 5.0v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition v oh output high voltage 2.6 2.6 2.6 v i oh = 24ma v ol output low voltage 0.5 0.5 0.5 v i ol = 48ma ios output short circuit current ma see note 1 1. the outputs must not be shorted to ground, as this will result in permanent damage to the device. the high drive outputs of t his device do not include a limiting ios resistor. ttl dc characteristics (vt = ve = 5.0 v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition v ih v il input high voltage input low voltage 2.0 0.8 2.0 0.8 2.0 0.8 v i ih input high current 20 100 20 100 20 100 m a v in = 2.7 v v in = 7.0 v i il input low current 0.6 0.6 0.6 ma v in = 0.5 v v oh output high voltage 2.5 2.0 2.5 2.0 2.5 2.0 v i oh = 3.0 ma i oh = 24 ma v ol output low voltage 0.5 0.5 0.5 v i ol = 24 ma v ik input clamp voltage 1.2 1.2 1.2 v i in = 18 ma 10h pecl dc characteristics (ivt = ovt = vcce = 5.0v 5%) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit notes i ih input high current 225 175 175 m a i il input low current 0.5 0.5 0.5 m a v ih input high voltage 3.83 4.16 3.87 4.19 3.94 4.28 v ivt = ivo = vcce = 5.0v ( 1 ) v il input low voltage 3.05 3.52 3.05 3.52 3.05 3.555 v ivt = ivo = vcce = 5.0v ( 1 ) v bb output reference voltage 3.62 3.73 3.65 3.75 3.69 3.81 v ivt = ivo = vcce = 5.0v ( 1 ) 100h pecl dc characteristics (ivt = ovt = vcce = 5.0v 5%) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit notes i ih input high current 225 175 175 m a i il input low current 0.5 0.5 0.5 m a v ih input high voltage 3.835 4.12 3.835 4.12 3.835 3.835 v ivt = ivo = vcce = 5.0v ( 1 ) v il input low voltage 3.19 3.525 3.19 3.525 3.19 3.525 v ivt = ivo = vcce = 5.0v ( 1 ) v bb output reference voltage 3.62 3.74 3.62 3.74 3.62 3.74 v ivt = ivo = vcce = 5.0v ( 1 ) 1. ecl v ih , v il and v bb are referenced to vcce and will vary 1:1 with the power supply. the levels shown are for ivt = ivo = vcce = 5.0v
mc10h646, mc100h646 http://onsemi.com 4 dc characteristics (ivt = ovt = vcce = 5.0v 5%) 0 c 25 c 85 c symbol characteristic min max min typ max min max unit condition i ccl power supply current 185 166 185 185 ma total all ovt, ivt, and vcce pins i cch 175 154 175 175 ma i ccz 210 210 210 ac characteristics (ivt = ovt = vcce = 5.0v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition t plh propagation delay eclk to q tclk to q 4.8 5.1 5.8 6.4 5.0 5.3 6.0 6.4 5.6 5.7 6.6 7.0 ns t phl propagation delay eclk to q tclk to q 4.4 4.7 5.4 6.0 4.4 4.8 5.4 5.9 4.8 5.2 5.8 6.5 ns t sk(o) output skew q0, q3, q4, q7 q1, q2, q5 q0q7 350 350 500 350 350 500 350 350 500 ps note 1, 6 t sk(pr) process skew eclk to q tclk to q 1.0 1.3 1.0 1.1 1.0 1.3 ns note 2, 6 t sk(p) pulse skew d t plh t phl 1.0 1.0 1.0 ns t r , t f rise/fall time 0.3 1.5 0.3 1.5 0.3 1.5 ns t pw output pulse width 66mhz @ 2.0v 66mhz @ 0.8v 60mhz @ 2.0v 60mhz @ 0.8v 5.5 5.5 6.0 6.0 5.5 5.5 6.0 6.0 5.5 5.5 6.0 6.0 ns note 3, 6 t stability clock stability 75 75 75 ps note 4, 6 f max maximum input frequency 80 80 80 mhz note 5, 6 1. output skew defined for identical output transitions. 2. process skew is valid for v cc = 5.0v 5%. 3. parameters guaranteed by t sk(p) and t r , t f specification limits. 4. clock stability is the period variation between two successive rising edges. 5. for series terminated lines. see applications section for f max enhancement techniques. 6. all ac specifications tested driving 50 w series terminated transmission lines at 80mhz.
mc10h646, mc100h646 http://onsemi.com 5 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue d notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum t, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). n m l v w d d y brk 28 1 view s s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s lm m 0.007 (0.180) n s t t b s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t u s lm m 0.007 (0.180) n s t z g1 x view dd s lm m 0.007 (0.180) n s t k1 view s h k f s lm m 0.007 (0.180) n s t dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 1.02
mc10h646, mc100h646 http://onsemi.com 6 notes
mc10h646, mc100h646 http://onsemi.com 7 notes
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